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march 2015 docid024551 rev 4 1 / 14 this is information on a product in full production. www.st.com STL90N10F7 n - channel 100 v, 0.007 typ., 70 a stripfet? f7 power mosfet in a powerflat? 5x6 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STL90N10F7 100 v 0.008 70 a 100 w ? among the lowest r ds(on) on the market ? excellent figure of merit (fom) ? low c rss /c iss ratio for emi immunity ? high avalanche ruggedness applications ? switching applications description this n - channel power mosfet utilizes stripfet ? f7 technology with an enhanced trench gate structure that results in very low on - state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. table 1: device summary order code marking package packing STL90N10F7 90n10f7 powerflat? 5x6 tape and reel 1 2 3 4 p o werfl a t? 5 x 6
contents STL90N10F7 2 / 14 docid024551 rev 4 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.1 electrical characteristics (curves) ...................................................... 6 3 test circuits ..................................................................................... 8 4 package information ....................................................................... 9 4.1 powerflat? 5x6 type r package information ................................ 9 4.2 powerflat? 5x6 packing information ........................................... 11 5 revision history ............................................................................ 13
STL90N10F7 electrical ratings docid024551 rev 4 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - source voltage 100 v v gs gate - source voltage 20 v i d (1) drain current (continuous) at t c = 25 c 70 a i d (1) drain current (continuous) at t c = 100 c 50 a i d (2) drain current (continuous) at t pcb = 25 c 16 a i d (2) drain current (continuous) at t pcb = 100 c 11 a i dm (1) (3) drain current (pulsed) 280 a i dm (2) (3) drain current (pulsed) 64 a p tot (1) total dissipation at t c = 25 c 100 w p tot (2) total dissipation at t pcb = 25 c 5 w e as (4) single pulse avalanche energy 300 mj t stg storage temperature - 55 to 175 c t j maxi mum junction temperature 175 c notes: (1) this value is rated according to r thj - c . (2) this value is rated according to r thj - pcb . (3) pulse width is limited by safe operating area. (4) starting t j = 25 c, i d = 10 a, v dd = 50 v. table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 1.5 c/w r thj - pcb (1) thermal resistance junction - pcb 31 notes: (1) when mounted on 1 inch2, 2 oz. cu fr - 4 board
electrical characteristics STL90N10F7 4 / 14 docid024551 rev 4 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 2 50 a 100 v i dss zero gate voltage drain current v gs = 0 v, v ds = 100 v 1 a v gs = 0 v, v ds = 100 v, t c = 125 c 100 a i gss gate - body leakage current v ds = 0 v, v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2.5 3.5 4.5 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 8 a 0.007 0.008 table 5: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 50 v, f = 1 mhz, v gs = 0 v - 3100 4030 pf c oss output capacitance - 700 910 pf c rss reverse transfer capacitance - 45 58 pf q g total gate charge v dd = 50 v, i d = 16 a, v gs = 10 v (see figure 14: "gate charge test circuit" ) - 45 60 nc q gs gate - source charge - 18 nc q gd gate - drain cha rge - 13 nc table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 50 v, i d = 8 a r g = 4.7 , v gs = 10 v (see figure 13: "switching times test circuit for resistive load" and figure 18: "switching time waveform" ) - 19 - ns t r rise time - 32 - ns t d(off) turn - off- delay t ime - 36 - ns t f fall time - 13 - ns
STL90N10F7 electrical characteristics docid024551 rev 4 5 / 14 table 7: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 16 a i sdm (1) source - drain current (pulsed) - 64 a v sd (2) forward on voltage v gs = 0 v, i sd = 16 a - 1.1 v t rr reverse recovery time i sd = 16 a, di/dt = 100 a/s, v dd = 80 v, t j = 150 c (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 70 90 ns q rr reverse recovery charge - 125 nc i rrm reverse recovery current - 3.6 a notes: (1) pulse width is limited by safe operating area . (2) pulse test: pulse duration = 300 s, duty cycle 1.5% .
electrical characteristics STL90N10F7 6 / 14 docid024551 rev 4 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gat e - source voltage figure 7 : static drain - source on - resistance
STL90N10F7 electrical characteristics docid024551 rev 4 7 / 14 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : source - drain diode forward characteristics
test circuits STL90N10F7 8 / 14 docid024551 rev 4 3 test circuits figure 13 : switching times test circuit for resistive load figure 14 : gate charge test circuit figure 15 : test circuit for inductive load switching and diode recovery times figure 16 : unclamped inductive load test circuit figure 17 : unclamped inductive waveform figure 18 : s witching time waveform am01469v1 v dd 47 k 1 k 47 k 2.7 k 1 k 12 v v i v gs 2200 f p w i g = const 100 100 nf d.u.t. v g am01470v1 a d d.u. t . s b g 25 a a b b r g g f ast diode d s l=100 h f 3.3 1000 f v dd d.u. t . v (b r )d s s v dd v dd v d i dm i d am01472v1 am01473v1 0 v gs 90% v ds t on 90% 10% 90% 10% t d(on) t r t t d(off) t f 10% 0 off
STL90N10F7 package information docid024551 rev 4 9 / 14 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their l evel of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 powerflat? 5x6 type r package information figure 19 : powerflat? 5x6 type r package outline
package information STL90N10F7 10 / 14 docid024551 rev 4 table 8: powerflat? 5x6 type r mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 e 5.95 6.15 6 .35 d2 4.11 4.31 e 1.27 l 0.60 0.80 k 1.275 1.575 e3 2.35 2.55 e4 0.40 0.60 e5 0.08 0.28 figure 20 : powerflat? 5x6 recommended footprint (dimensions are in mm)
STL90N10F7 package information docid024551 rev 4 11 / 14 4.2 powerflat? 5x6 packing information figure 21 : powerflat? 5x6 tape (dimensions are in mm) figure 22 : powerflat? 5x6 package orientation in carrier tape measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centerline of sprocket hole to centerline of pocket. (i) (ii) (iii) 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 4.00.1 (ii) p 0 y y section y - y c l p1(8.000.1) do d1 e 1 (0.30 t re f .r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_ t ape_rev_c
package information STL90N10F7 12 / 14 docid024551 rev 4 figure 23 : powerflat? 5x6 reel
STL90N10F7 revision history docid024551 rev 4 13 / 14 5 revision history table 9: document revision history date revision changes 16- apr- 2013 1 first release. 06- mar -2014 2 ? modified: r ds(on) value in cover page ? modified: v gs(th) values in table 4 ? modified: r ds(on) typ. and max values in table 4 ? modified: typical values in table 5, 6 and 7 ? updated: section 4: package mechanical data ? added: section 2.1: electrical characterist ics (curves) ? updated: section 4: package mechanical data ? document status promoted from preliminary data to production data 16- dec - 2014 3 ? updated title, features and description in cover page. ? updated r ds(on) values and figure 7: static drain - sourc e onresistance. 17- mar -2015 4 ? text edits throughout document ? updated cover page title description ? updated cover page features table ? in table 2. absolute maximum ratings, added "e as " information and footnote 4 ? in table 3. thermal data, added footno te 1 ? renamed table 4. static (was on/off states) ? updated table 5. dynamic ? updated table 7. source drain diode ? in section 2.1 electrical characteristics (curves), updated figures 2, 3, 10 and 11 ? updated and renamed section 4 package information
STL90N10F7 14 / 14 docid024551 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and imp rovements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant inf ormation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the t ime of order acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for applicati on assistance or the design of purchasers? products. no license, express or implied, to any inte llectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st f or such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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